1. Technical Field
The present disclosure relates to alignment structures formed on a plurality of wafers configured to be aligned to form a multichip stack in a single package.
2. Description of the Related Art
As consumer demand increases for smaller multifunction devices, manufacturers face significant challenges to integrate different semiconductor technologies on a single die. Multichip packages have become increasingly popular to increase device density and to combine traditionally incompatible technologies, such as logic, memory, and micro-electromechanical systems (MEMS). For example, as cell phones include more functions, such as personal entertainment systems, manufacturers look for ways to integrate multiple technologies, such as SRAM, DRAM, flash, logic, analog, and radio frequency, into one relatively thin package.
Multichip packages also address some of the limitations that have arisen with respect to high density scaling. In multichip packages the dies may be aligned and bonded at the wafer level or as individual die. Each of the dies to be included in a multichip package is formed on a single wafer based on a particular technology. For example, one die may be manufactured to be a processor using one process technology and then packaged with a MEMS sensor, which was separately manufactured on another wafer using different process technology.
These vertically stacked chips formed from multiple die offer improved density and performance. The challenges to integrate traditionally incompatible processes on a single wafer are avoided by forming incompatible technologies on individual wafers and packaging them in the single package.